Semiconductor technology - Topics

Will stacked CFETs be the next step after nanosheet transistors? Carbon nanotube transistors: what is left to solve before they beat silicon? FinFET to gate-all-around: what does the nanosheet actually fix? Why does silicon refuse to emit light and what do engineers use instead? Silicon spin qubits built in an ordinary CMOS foundry High-NA EUV: what does the smaller feature buy and what does it cost? Backside power delivery: why move the wires under the transistors? How does a silicon photonics modulator reach 100 Gbps on a CMOS-compatible process? Molybdenum and ruthenium interconnects: why replace copper? Why do process node names no longer match any real dimension? What does gate pitch tell you that a node name does not? At what point does a new node stop being worth the design cost? Perovskite tandem cells: what an efficiency record still hides about stability What does design technology co-optimization mean in practice? Why did the industry stop scaling supply voltage at every node? Why do SRAM cells stop scaling before logic does? How do you fairly compare one foundry's 3nm with another foundry's 3nm? What is the theoretical efficiency limit of a single-junction solar cell and what beats it?